Design and Test-Verification of a Single-Cycle RISC-V Microprocessor on FPGA

This paper presents the design and testing procedure of a single-core Reduced Instruction Set Computer V (RISC-V) microprocessor implemented on a Spartan 7 Xilinx FPGA, utilizing the CMOD S7 development board. The synthesized core is based on the RISC-V 32-bit Integer (RV32I) module of RISC-V ISA and operates at a target clock frequency of 12 MHz, providing an instruction per clock (IPC) of 1. Challenges related to the single-cycle implementation are discussed, with a focus on addressing memory access complexities. Extensive testing has been conducted on the core, successfully passing all official RISC-V integer set tests. The FPGA resource utilization for this implementation is low, requiring 4671 Look-Up Tables (LUT), 2.5 Block RAM (BRAM), and 3964 Flip Flops.