A single-loop filter architecture based on positive- and negative-impedance voltage followers yields a drastic reduction in power consumption with respect to the state of the art. The architecture is demonstrated by a filter for ultra wide-band receivers implemented in 0.13μm CMOS. The 6th-order filter has a 280MHz cut-off frequency, an 11dBm IIP3, -140dBm input-referred noise and draws 100μA from a 1.2V supply. ©2008 IEEE.
D'Amico, S., DE MATTEIS, M., Baschirotto, A. (2008). A 6th-order 100μA 280MHz source-follower-based single-loop continuous-time filler. In Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International (pp.72-596). Institute of Electrical and Electronics Engineers Inc. [10.1109/ISSCC.2008.4523062].
A 6th-order 100μA 280MHz source-follower-based single-loop continuous-time filler
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2008
Abstract
A single-loop filter architecture based on positive- and negative-impedance voltage followers yields a drastic reduction in power consumption with respect to the state of the art. The architecture is demonstrated by a filter for ultra wide-band receivers implemented in 0.13μm CMOS. The 6th-order filter has a 280MHz cut-off frequency, an 11dBm IIP3, -140dBm input-referred noise and draws 100μA from a 1.2V supply. ©2008 IEEE.
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