In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.

Baschirotto, A., Chironi, V., Cocciolo, G., D’Amico, S., DE MATTEIS, M., Delizia, P. (2009). Low Power Analog Design in Scaled Technologies. In Topical Workshop on Electronics for Particle Physics (TWEPP-09).

Low Power Analog Design in Scaled Technologies

BASCHIROTTO, ANDREA;DE MATTEIS, MARCELLO;
2009

Abstract

In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.
paper
CMOS, analog design
English
Topical Workshop on Electronics for Particle Physics (TWEPP-09)
Topical Workshop on Electronics for Particle Physics (TWEPP-09)
2009
none
Baschirotto, A., Chironi, V., Cocciolo, G., D’Amico, S., DE MATTEIS, M., Delizia, P. (2009). Low Power Analog Design in Scaled Technologies. In Topical Workshop on Electronics for Particle Physics (TWEPP-09).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/8914
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