In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.
Baschirotto, A., Chironi, V., Cocciolo, G., D’Amico, S., De Matteis, M., & Delizia, P. (2009). Low Power Analog Design in Scaled Technologies. In Topical Workshop on Electronics for Particle Physics (TWEPP-09).
Citazione: | Baschirotto, A., Chironi, V., Cocciolo, G., D’Amico, S., De Matteis, M., & Delizia, P. (2009). Low Power Analog Design in Scaled Technologies. In Topical Workshop on Electronics for Particle Physics (TWEPP-09). | |
Tipo: | paper | |
Carattere della pubblicazione: | Scientifica | |
Titolo: | Low Power Analog Design in Scaled Technologies | |
Autori: | Baschirotto, A; Chironi, V; Cocciolo, G; D’Amico, S; De Matteis, M ; Delizia, P | |
Autori: | ||
Data di pubblicazione: | 2009 | |
Lingua: | English | |
Nome del convegno: | Topical Workshop on Electronics for Particle Physics (TWEPP-09) | |
Appare nelle tipologie: | 02 - Intervento a convegno |