The CLARO-CMOS is a prototype ASIC primarily designed for single-photon counting with multi-anode photomultipliers (Ma-PMTs), that found applications also in the read-out of silicon photomultipliers (SiPMs) and microchannel plates (MCPPMTs). The chip allows fast photon counting up to 40 MHz, with a power consumption of less than 1 mW per channel. The prototype is realised in a 0.35 micron CMOS technology. In the LHCb RICH environment, over ten years of operation at the nominal luminosity for the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neutron equivalent cm -2 and a total ionising dose of 400 krad. We present the results of multi-step irradiation tests with neutrons and with X-rays up to the fluence of 1014 cm-2 and 4 Mrad, respectively, including measurement of single event effects during irradiation and the evaluation of chip performance before and after each irradiation step. © 2013 IEEE.
Fiorini, M., Andreotti, M., Baldini, W., Calabrese, R., Carniti, P., Ramusino, A., et al. (2013). Radiation hardness of the CLARO-CMOS, a prototype ASIC for low power and fast single-photon counting in 0.35 micron CMOS technology. In IEEE Nuclear Science Symposium Conference Record (pp.1-2). Institute of Electrical and Electronics Engineers Inc. [10.1109/NSSMIC.2013.6829722].
Radiation hardness of the CLARO-CMOS, a prototype ASIC for low power and fast single-photon counting in 0.35 micron CMOS technology
CARNITI, PAOLO;GIACHERO, ANDREA;GOTTI, CLAUDIO;MAINO, MATTEO;PESSINA, GIANLUIGI EZIO;
2013
Abstract
The CLARO-CMOS is a prototype ASIC primarily designed for single-photon counting with multi-anode photomultipliers (Ma-PMTs), that found applications also in the read-out of silicon photomultipliers (SiPMs) and microchannel plates (MCPPMTs). The chip allows fast photon counting up to 40 MHz, with a power consumption of less than 1 mW per channel. The prototype is realised in a 0.35 micron CMOS technology. In the LHCb RICH environment, over ten years of operation at the nominal luminosity for the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neutron equivalent cm -2 and a total ionising dose of 400 krad. We present the results of multi-step irradiation tests with neutrons and with X-rays up to the fluence of 1014 cm-2 and 4 Mrad, respectively, including measurement of single event effects during irradiation and the evaluation of chip performance before and after each irradiation step. © 2013 IEEE.
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