Digital Baseband Architecture and Control Logic for Sub-GHz Mixed-Signal TR-PPM Transmitter ASIC

This work presents the digital baseband architecture and control logic for a low-power Transmitted-Reference Pulse-Position Modulation (TR-PPM) transmitter ASIC operating at 433.92 MHz. The TR-PPM framework mitigates synchronization challenges and performance degradation in multipath channels by embedding a reference pulse within each symbol period, enabling noncoherent detection and enhanced link robustness without complex channel estimation. The proposed digital subsystem implements a fully configurable data-path, including packet framing, Cyclic Redundancy Check (CRC) generation, and TR-PPM symbol mapping. A frame controller orchestrates timing, reference-pulse alignment, and enable sequencing of Radio Frequency (RF) blocks (Phase-Locked Loop (PLL), Power Amplifier (PA), and reference oscillator) to ensure minimal active duty cycle and reduced energy consumption. The modular Register Transfer Level (RTL) design, verified through system-level simulations, integrates seamlessly with the analog/RF core, achieving reliable frame generation and deterministic timing control. The result is a low-cost digital baseband that leverages RF macro enable/disable capability to deliver energy-efficient, PPM transmission for ultra-low-power Internet of Things (IoT) nodes.