A complete IC with a innovative Sample & Hold structure to be used in aggressive low-duty cycle scheme for power reduction approach is proposed. The circuit is autonomous, since it includes a fully-integrated current and frequency generator. All digital logics are current limited to reduce cross-bar current. The S/H is able to multiply the input voltage and to hold the resulting voltage for 100msec with a negligible droop rate (70mV/sec at 140°C). For extremely high temperature up to 175°C, the leakage current increase results in a droop rate of 570mV/sec that produces a maximum 5.7% error. The full circuit consumes an average current of 460nA, enabling turning-off the reference voltage generator.
Pulcini, L., Del Croce, P., Baschirotto, A. (2026). A Complete Low-Duty-Cycle S/H System with 100ms Hold Time at 175°C. In 2026 IEEE International Symposium on Circuits and Systems (ISCAS) (pp.3305-3309). IEEE [10.1109/ISCAS66217.2026.11562116].
A Complete Low-Duty-Cycle S/H System with 100ms Hold Time at 175°C
Pulcini L.;Baschirotto A.
2026
Abstract
A complete IC with a innovative Sample & Hold structure to be used in aggressive low-duty cycle scheme for power reduction approach is proposed. The circuit is autonomous, since it includes a fully-integrated current and frequency generator. All digital logics are current limited to reduce cross-bar current. The S/H is able to multiply the input voltage and to hold the resulting voltage for 100msec with a negligible droop rate (70mV/sec at 140°C). For extremely high temperature up to 175°C, the leakage current increase results in a droop rate of 570mV/sec that produces a maximum 5.7% error. The full circuit consumes an average current of 460nA, enabling turning-off the reference voltage generator.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
