2.77 kV/m/s2Sensitivity Digital Demodulator-Decimator-Filter on Xilinx Spartan-7 FPGA for Sub-Hz Aerospace Nano-Gravimetry Accelerometers Down to 10 nm/s2

Nano-gravimetry accelerometer readout front ends for aerospace gravimetry measurements require both accurate analog and digital signal processing to extract with ultra-low noise power (<5 nVRMS at 1 Hz bandwidth) the weak sub-Hz acceleration signal. To migrate toward fully integrated monolithic silicon systems, such a weak acceleration signal requires advanced analog and digital signal processing techniques: analog low-noise amplification and digitization and digital precise demodulation and filtering with a strong (×100 power with respect to sub-Hz acceleration) rejection of the nonscientifically relevant out-of-band acceleration interferers. This letter focuses on the digital signal conditioning section composed of demodulation, decimation, and filtering stages. To validate the proposed design, we designed an analog front end that amplifies, filters, and digitizes acceleration signals produced by an emulated sensor. The complete design and behavioral/electrical characterization are presented and deployed on a Digilent CMOD S7 35T evaluation board mounting the cost-optimized Spartan-7 Field Programmable Gate Array (FPGA). The digital demodulator, decimator, and filter stages reconstruct the minimum amplified signal of 10 nm/s2 at 1 Hz with a measured signal-to-noise ratio of 12.2 and 12.4 dB with and without the out-of-band interferers, respectively.