This paper presents a low-power 433.92MHz Pulse Position Modulation (PPM) transmitter designed using the TSMC 65nm CMOS technology. The transmitter primarily comprises a Phase-Locked Loop (PLL) frequency synthesizer, a Pierce Oscillator responsible for generating the PLL reference clock, and a Class-E power amplifier (PA). Notably, all components of the implemented transmitter ASIC feature enable/disable functionality to facilitate Pulse Position Modulation (PPM) implementation. While the transmitter is fully integrated on a chip, excluding the PI load impedance matching network and load capacitors of the Pierce Oscillator, post-simulation results indicate a PLL locked time of approximately 5μs. The transmitter exhibits a power consumption of 140.94mA at a 1.2-volt supply, with the PA delivering an output power of +16.9dBm. The overall footprint of the transmitter is compact, measuring 0.8mm × 1mm, inclusive of ESD pads.

Amin, S., Baschirotto, A. (2025). A Fully Integrated 433.92 MHz PPM Transmitter with 16.9 dBm Output Power and 210 nJ/Bit Efficiency. In 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp.1-4). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS61496.2024.10849200].

A Fully Integrated 433.92 MHz PPM Transmitter with 16.9 dBm Output Power and 210 nJ/Bit Efficiency

Amin S. U.
Primo
;
Baschirotto A.
Ultimo
2025

Abstract

This paper presents a low-power 433.92MHz Pulse Position Modulation (PPM) transmitter designed using the TSMC 65nm CMOS technology. The transmitter primarily comprises a Phase-Locked Loop (PLL) frequency synthesizer, a Pierce Oscillator responsible for generating the PLL reference clock, and a Class-E power amplifier (PA). Notably, all components of the implemented transmitter ASIC feature enable/disable functionality to facilitate Pulse Position Modulation (PPM) implementation. While the transmitter is fully integrated on a chip, excluding the PI load impedance matching network and load capacitors of the Pierce Oscillator, post-simulation results indicate a PLL locked time of approximately 5μs. The transmitter exhibits a power consumption of 140.94mA at a 1.2-volt supply, with the PA delivering an output power of +16.9dBm. The overall footprint of the transmitter is compact, measuring 0.8mm × 1mm, inclusive of ESD pads.
paper
Class-E Power Amplifier (PA); ISM Band Transmitter; Phase Lock Loop (PLL); Pulse Position Modulation (PPM);
English
2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) - 18-20 November 2024
2024
2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
9798350377200
28-gen-2025
2025
1
4
none
Amin, S., Baschirotto, A. (2025). A Fully Integrated 433.92 MHz PPM Transmitter with 16.9 dBm Output Power and 210 nJ/Bit Efficiency. In 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp.1-4). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS61496.2024.10849200].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/545042
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