This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage. © 2013 IEEE.
Pasca, M., Chironi, V., D'Amico, S., DE MATTEIS, M., Baschirotto, A. (2013). A 12dBm IIP3 reconfigurable mixer for high/low band IR-UWB receivers. In Conference Proceedings - 9th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2013 (pp.81-84) [10.1109/PRIME.2013.6603101].
A 12dBm IIP3 reconfigurable mixer for high/low band IR-UWB receivers
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2013
Abstract
This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage. © 2013 IEEE.
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