A calibration free, high resolution second-order multi-channel Incremental A-to-D-Converter with multi-level quantizer is presented. The system is designed for biomedical application and combines the advantages of low oversampling ratio with SC design solution, like multi bit topology and accurate opamp design. An optimal decimation filter to minimize the weighted sum of thermal and quantization noise is used. In this paper is presented the schematic level implementation of the system in a 1.2 V 90 nm CMOS Technology and the preliminary simulation shows a 56.4 dB signal-to-noise-distortion within a 500 kHz bandwidth at a 16 MHz sample frequency
Cavallo, D., DE MATTEIS, M., Ronchi, M., Leggeri, G., Baschirotto, A. (2013). A very low OSR 90nm 1MS/s incremental ΣΔ ADC. In Conference Proceedings - 9th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2013 (pp.37-40) [10.1109/PRIME.2013.6603106].
A very low OSR 90nm 1MS/s incremental ΣΔ ADC
CAVALLO, DOMENICO;DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2013
Abstract
A calibration free, high resolution second-order multi-channel Incremental A-to-D-Converter with multi-level quantizer is presented. The system is designed for biomedical application and combines the advantages of low oversampling ratio with SC design solution, like multi bit topology and accurate opamp design. An optimal decimation filter to minimize the weighted sum of thermal and quantization noise is used. In this paper is presented the schematic level implementation of the system in a 1.2 V 90 nm CMOS Technology and the preliminary simulation shows a 56.4 dB signal-to-noise-distortion within a 500 kHz bandwidth at a 16 MHz sample frequency
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