The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13 mu m technology, consumes 350 mu W (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate
Vergine, T., DE MATTEIS, M., D'Amico, S., Chironi, V., Marchioro, A., Kloukinas, K., et al. (2013). A 32-channel 12-bits single slope A-to-D converter for LHC environment. In Proceedings of 2013 International Conference on IC Design & Technology (ICICDT 2013) (pp.139-142). IEEE [10.1109/ICICDT.2013.6563322].
A 32-channel 12-bits single slope A-to-D converter for LHC environment
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2013
Abstract
The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13 mu m technology, consumes 350 mu W (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate
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