In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 mu m CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels. Each channel performs the charge-vs-time conversion, and then the signal is definitively converted into digital domain. For this aim a Charge-Sensitive Preamplifier (CSP), and a Charge-to-Time Converter (CTC) are implemented. An automatic on-chip calibration circuit is also included, in order to compensate CMOS technological process/temperature variations. The system is able to manage a 15 pF detector capacitance. The maximum count rate is 4.10(6) counts-per-second (cps) and the power consumption is 3.8 mW/ch. The Equivalent Noise Charge (ENC) is 418 e(-). The front-end compares favorably with the state-of-the-art
Pezzotta, A., Costantini, A., DE BLASI, M., DE MATTEIS, M., Gorini, G., Murtas, F., et al. (2013). A CMOS 0.13μm read-out front-end for triple-gas-electron-multiplier detectors. In Proceedings of the 2013 5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI 2013 (pp.65-70). IEEE [10.1109/IWASI.2013.6576054].
A CMOS 0.13μm read-out front-end for triple-gas-electron-multiplier detectors
PEZZOTTA, ALESSANDRO;COSTANTINI, ANDREA;DE BLASI, MARCO;DE MATTEIS, MARCELLO;GORINI, GIUSEPPE;BASCHIROTTO, ANDREA
2013
Abstract
In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 mu m CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels. Each channel performs the charge-vs-time conversion, and then the signal is definitively converted into digital domain. For this aim a Charge-Sensitive Preamplifier (CSP), and a Charge-to-Time Converter (CTC) are implemented. An automatic on-chip calibration circuit is also included, in order to compensate CMOS technological process/temperature variations. The system is able to manage a 15 pF detector capacitance. The maximum count rate is 4.10(6) counts-per-second (cps) and the power consumption is 3.8 mW/ch. The Equivalent Noise Charge (ENC) is 418 e(-). The front-end compares favorably with the state-of-the-art
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
