A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 56.9dB signal-to-noise and distorsion ratio (SNDR), 58.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a fullscale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm(2) die area
Donno, A., D'Amico, S., DE MATTEIS, M., Baschirotto, A. (2013). A 10-b 100-MSPS low power pipeline ADC for high energy physics experiments. In 2013 9TH CONFERENCE ON PH. D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2013) (pp.201-204) [10.1109/PRIME.2013.6603152].
A 10-b 100-MSPS low power pipeline ADC for high energy physics experiments
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2013
Abstract
A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 56.9dB signal-to-noise and distorsion ratio (SNDR), 58.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a fullscale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm(2) die area
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