Analog Techniques for Low-power High-Performance Switched-Capacitor Sigma-Delta Modulators

This paper presents some innovative techniques for the implementation of high-performance Switched-Capacitor Sigma-Delta Modulators (SC-SDMs). The case of a single-bit single-loop topology is studied, where the main performance limitations are from the first integrator. The performance of this block in terms of linearity and noise have been analyzed and significant improvements have been achieved with new techniques, with limited or zero power consumption increase. These techniques aim to tackle some performance limitations, such as the slew-rate and operational amplifier noise folding. When applied to a 2nd-order SC-SDM, they enable to achieve a Dynamic Range of 115 dB (i.e. 18.8 bits) on a 1kHz bandwidth, with a power consumption of 165 μW from a 1.2 V supply.