Continuous tracking of heart activity from an Electrocardiogram (ECG) signal to assist physicians in treating Cardio Vascular Disease (CVD) requires a miniaturized and power-efficient design for long-time continuous monitoring. The work presents an ultra-low-power bio-potential acquisition and 11b successive approximation register (SAR) analog to digital converter (ADC) to acquire clean ECG signal and digitized data for further on-sensor processing, respectively. The designed low-noise amplifier (LNA) targets a wearable environment utilizing an AC coupled chopper technique to reject rail-to-rail electrode DC offset (EDO), 50/60 Hz interference, and mitigate flicker noise. The proposed analog front end (AFE) is implemented utilizing a CMOS 180nm technology and consumes 1.3uA of current while operating @ 1V. The system achieves NEF and input-referred noise of 2.67 and 50nV/√Hz, respectively, with an effective number of bits (ENOB) of 10.1.
Ali Shah, S., Ali, M., Bin Altaf, M. (2022). A Low-Power Bio-potential acquisition for the wearable shockable Electrocardiogram (ECG) System. In 2021 1st International Conference on Microwave, Antennas & Circuits (ICMAC). Institute of Electrical and Electronics Engineers Inc. [10.1109/icmac54080.2021.9678263].
A Low-Power Bio-potential acquisition for the wearable shockable Electrocardiogram (ECG) System
Ali Shah, Syed Adeel;
2022
Abstract
Continuous tracking of heart activity from an Electrocardiogram (ECG) signal to assist physicians in treating Cardio Vascular Disease (CVD) requires a miniaturized and power-efficient design for long-time continuous monitoring. The work presents an ultra-low-power bio-potential acquisition and 11b successive approximation register (SAR) analog to digital converter (ADC) to acquire clean ECG signal and digitized data for further on-sensor processing, respectively. The designed low-noise amplifier (LNA) targets a wearable environment utilizing an AC coupled chopper technique to reject rail-to-rail electrode DC offset (EDO), 50/60 Hz interference, and mitigate flicker noise. The proposed analog front end (AFE) is implemented utilizing a CMOS 180nm technology and consumes 1.3uA of current while operating @ 1V. The system achieves NEF and input-referred noise of 2.67 and 50nV/√Hz, respectively, with an effective number of bits (ENOB) of 10.1.
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