Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators

In audio applications such as Bluetooth and USB-C, where low power consumption and tight surface budget represent the greater constraints, continuous-time sigma-delta modulators (CTSDM) are the most interesting solution for data conversion. The main concern is their particular sensitivity to jitter which makes using specific countermeasures mandatory. Willing to use FIR-DAC single bit strategy to limit jitter impact, this paper wants to highlight the importance of a proper quantitative jitter analysis preliminary to design, which in prior works has always been made with approximations. To do so, a fourth order single-bit CTSDM clocked at 3.072MHz is also presented, showing that properly sizing the FIR-DAC with this method allow to reach the desired Dynamic Range (DR) of at least 100dB over 20kHz without taking certain kind of risks.