This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4 m devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.
Taralkar, A., Conzatti, F., Malcovati, P., Baschirotto, A. (2021). A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp.215-218). IEEE [10.1109/ESSCIRC53450.2021.9567825].
A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter
Baschirotto A.
2021
Abstract
This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4 m devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.
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