This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 W from 1.1 V and performing -6 dBm in-band Input IP3 at 20 dB passband gain.

De Matteis, M., Baschirotto, A., Vallicelli, E. (2021). 309-W 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp.339-342). Institute of Electrical and Electronics Engineers Inc. [10.1109/ESSCIRC53450.2021.9567852].

309-W 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS

De Matteis M.;Baschirotto A.;Vallicelli E. A.
2021

Abstract

This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 W from 1.1 V and performing -6 dBm in-band Input IP3 at 20 dB passband gain.
paper
Analog Filters; Analog Integrated Circuits; Low Noise Amplifiers;
English
47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 - SEP 06-09, 2021
2021
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
9781665437479
2021
339
342
none
De Matteis, M., Baschirotto, A., Vallicelli, E. (2021). 309-W 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp.339-342). Institute of Electrical and Electronics Engineers Inc. [10.1109/ESSCIRC53450.2021.9567852].
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/471634
Citazioni
  • Scopus 2
  • ???jsp.display-item.citation.isi??? 2
Social impact