The synergy between schematic and layout to optimize the performance of analog circuits in scaled technologies is addressed for the case of an innovative analog filter, developed in the 28nm node. This benchmark is a 75MHz 4th-order low-pass analog filter in 28nm-CMOS composed by two Active-RC Rauch biquadratic cells. The architecture is customized to properly operate in the challenging conditions of low VDD (0.9V) and low [VDD-VTH] space (≈ 0.4V) and overcoming the poor analog performance of the 28nm MOS devices. In these directions, aggressive opamp input and output CMFB are applied. The paper shows how layout could corrupt the high-frequency performance of the filter without specific solutions. Optimized and synergic design and layout solutions are validated by the experimental results. The filter consumes 2.68mW from a single 0.9V-VDD. 11.5dB IIP3 at 20&21MHz and 40dBc of THD at 20MHz, respectively are achieved, while performing 310µVRMS of integrated in band noise.
Ciciotti, F., Fary, F., De Matteis, M., Baschirotto, A. (2019). 28nm Implementation Aspects of a 0.9V 75MHz 4th-Order Rauch Analog Filter. In Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. [10.1109/ISCAS.2019.8702354].
28nm Implementation Aspects of a 0.9V 75MHz 4th-Order Rauch Analog Filter
De Matteis M.;Baschirotto A.
2019
Abstract
The synergy between schematic and layout to optimize the performance of analog circuits in scaled technologies is addressed for the case of an innovative analog filter, developed in the 28nm node. This benchmark is a 75MHz 4th-order low-pass analog filter in 28nm-CMOS composed by two Active-RC Rauch biquadratic cells. The architecture is customized to properly operate in the challenging conditions of low VDD (0.9V) and low [VDD-VTH] space (≈ 0.4V) and overcoming the poor analog performance of the 28nm MOS devices. In these directions, aggressive opamp input and output CMFB are applied. The paper shows how layout could corrupt the high-frequency performance of the filter without specific solutions. Optimized and synergic design and layout solutions are validated by the experimental results. The filter consumes 2.68mW from a single 0.9V-VDD. 11.5dB IIP3 at 20&21MHz and 40dBc of THD at 20MHz, respectively are achieved, while performing 310µVRMS of integrated in band noise.
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