This paper presents a continuous time voltage amplifier based on a classical MOS Transistor (MOST) input differential stage feeding a regulated cascode output stage. One of the most interesting aspects of the presented circuit is the introduction of complex conjugated poles in the output stage which together with a simple R-C network at the input of the differential stage allows to synthesize a 3rd-order low-pass Butterworth transfer function at 20 dB of passband gain. The proposed circuital technique has been validated by the design of a 3rd-order low-pass filter and amplifier in 28 nm CMOS technology. The proposed circuit has 5.2 nV/√Hz in-band Input Referred Noise (IRN) Power Spectral Density (PSD), -3.2 dBm Input 3rd-order Intercept Point (IIP3) at 20 dB passband gain and a final Signal-to-Noise-Ratio (SNR) of 60 dB. This solution is particularly efficient in terms of both power consumption and linearity while performing large SNR, as demonstrated by the final Figure-of-Merit of 159.2 dBJ-1.
La Gala, A., Baschirotto, A., Benedini, F., Stevenazzi, L., Vallicelli, E., De Matteis, M. (2023). 50-MHz-Bandwidth 850-μW-Power 60-dB-SNR Analog Amplifier with Complex Conjugated Poles. In Proceedings - IEEE International Symposium on Circuits and Systems. IEEE [10.1109/iscas46773.2023.10182100].
50-MHz-Bandwidth 850-μW-Power 60-dB-SNR Analog Amplifier with Complex Conjugated Poles
La Gala, Andrea;Baschirotto, Andrea;Benedini, Federica;Stevenazzi, Lorenzo;Vallicelli, Elia Arturo;De Matteis, Marcello
2023
Abstract
This paper presents a continuous time voltage amplifier based on a classical MOS Transistor (MOST) input differential stage feeding a regulated cascode output stage. One of the most interesting aspects of the presented circuit is the introduction of complex conjugated poles in the output stage which together with a simple R-C network at the input of the differential stage allows to synthesize a 3rd-order low-pass Butterworth transfer function at 20 dB of passband gain. The proposed circuital technique has been validated by the design of a 3rd-order low-pass filter and amplifier in 28 nm CMOS technology. The proposed circuit has 5.2 nV/√Hz in-band Input Referred Noise (IRN) Power Spectral Density (PSD), -3.2 dBm Input 3rd-order Intercept Point (IIP3) at 20 dB passband gain and a final Signal-to-Noise-Ratio (SNR) of 60 dB. This solution is particularly efficient in terms of both power consumption and linearity while performing large SNR, as demonstrated by the final Figure-of-Merit of 159.2 dBJ-1.File | Dimensione | Formato | |
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