A 130-nm CMOS high-side current sensor (CS) for peak-current dc-dc converters, operating with an input voltage up to 40 V is presented. A loop prebiasing technique is used to prevent the proposed sense-FET-based CS from losing its linear behavior, thus achieving fast response time and, hence, allowing operation of the dc-dc converter with short minimum on-time. The proposed circuit also exploits a feedback resistance emulation technique for preventing the feedback loop to open during the blanking time. The CS has been integrated within a complete 40-V peak-current dc-dc buck converter that achieves 1-mV/A load regulation and 0.1-mV/V line regulation performances, even with a minimum on-time of 51 ns, with a peak efficiency of 92.5%.
Kizas, T., Bergo, M., Capodivacca, G., Scandola, L., Malcovati, P., Baschirotto, A. (2022). A 51-ns Response-Time, Fully Integrated, High-Side Current Sensor for a 40-V 6-A dc-dc Converter. IEEE SOLID-STATE CIRCUITS LETTERS, 5, 300-303 [10.1109/LSSC.2022.3227980].
A 51-ns Response-Time, Fully Integrated, High-Side Current Sensor for a 40-V 6-A dc-dc Converter
Baschirotto A.
2022
Abstract
A 130-nm CMOS high-side current sensor (CS) for peak-current dc-dc converters, operating with an input voltage up to 40 V is presented. A loop prebiasing technique is used to prevent the proposed sense-FET-based CS from losing its linear behavior, thus achieving fast response time and, hence, allowing operation of the dc-dc converter with short minimum on-time. The proposed circuit also exploits a feedback resistance emulation technique for preventing the feedback loop to open during the blanking time. The CS has been integrated within a complete 40-V peak-current dc-dc buck converter that achieves 1-mV/A load regulation and 0.1-mV/V line regulation performances, even with a minimum on-time of 51 ns, with a peak efficiency of 92.5%.
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