A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1–5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mµ CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

Ryckaert, J., Verhelst, M., Badaroglu, M., D'Amico, S., De Heyn, V., Desset, C., et al. (2007). A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42(11), 2515-2527 [10.1109/JSSC.2007.907195].

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

BASCHIROTTO, ANDREA;
2007

Abstract

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1–5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mµ CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.
Articolo in rivista - Articolo scientifico
CMOS integrated circuits; Direct-conversion; Low-power electronics; Pulse-position modulation; Receivers; RF; ultra-wideband (UWB);
English
2515
2527
13
Ryckaert, J., Verhelst, M., Badaroglu, M., D'Amico, S., De Heyn, V., Desset, C., et al. (2007). A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42(11), 2515-2527 [10.1109/JSSC.2007.907195].
Ryckaert, J; Verhelst, M; Badaroglu, M; D'Amico, S; De Heyn, V; Desset, C; Nuzzo, P; Van Poucke, B; Wambacq, P; Baschirotto, A; Dehaene, W; Van der Plas, G
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/3821
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