Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segmentaddressed resulting in a very compact 0.007 mm2 chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz. © Springer Science+Business Media, LLC 2011.

Chironi, V., Debaillie, B., Baschirotto, A., Craninckx, J., Ingels, M. (2011). Direct Digital-RF Amplitude Modulator in CMOS 90nm. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 68(1), 21-31 [10.1007/s10470-011-9606-9].

Direct Digital-RF Amplitude Modulator in CMOS 90nm

BASCHIROTTO, ANDREA;
2011

Abstract

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segmentaddressed resulting in a very compact 0.007 mm2 chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz. © Springer Science+Business Media, LLC 2011.
Articolo in rivista - Articolo scientifico
transmitter
English
2011
68
1
21
31
none
Chironi, V., Debaillie, B., Baschirotto, A., Craninckx, J., Ingels, M. (2011). Direct Digital-RF Amplitude Modulator in CMOS 90nm. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 68(1), 21-31 [10.1007/s10470-011-9606-9].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/37733
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