The possibility of implementing the double-sampling (DS) technique in IIR first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows to design high-frequency SC filtering systems (an anti-aliasing SC decimator filter and a "core" DS-SC filter) where the op-amp speed requirements are the same in each block
Baschirotto, A., Castello, R., Montecchi, F. (1992). IIR Double-Sampled Switched-Capacitor Decimators for High-Frequency Applications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 39(4), 300-304 [10.1109/81.129459].
IIR Double-Sampled Switched-Capacitor Decimators for High-Frequency Applications
Baschirotto, A;
1992
Abstract
The possibility of implementing the double-sampling (DS) technique in IIR first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows to design high-frequency SC filtering systems (an anti-aliasing SC decimator filter and a "core" DS-SC filter) where the op-amp speed requirements are the same in each blockI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.