A 10bit SAR-ADC implemented in a 1.2V 0.13 mu m CMOS with 1V(ppiff)-FS, based on capacitive-charge redistribution can be programmed with F-s up-to-6MS/s, guaranteeing an ENOB > 9b with a SFDR > 74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoM approximate to 1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200 mu W and the FoM approximate to 0.1pJ/conv. This appears an attractive solution for embedded ADC
Borghetti, F., Nielsen, J., Ferragina, V., Malcovati, P., Andreani, P., Baschirotto, A. (2006). A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers. In ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (pp.500-503). 345 E 47TH ST, NEW YORK, NY 10017 USA : IEEE [10.1109/ESSCIR.2006.307499].
A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers
BASCHIROTTO, ANDREA
2006
Abstract
A 10bit SAR-ADC implemented in a 1.2V 0.13 mu m CMOS with 1V(ppiff)-FS, based on capacitive-charge redistribution can be programmed with F-s up-to-6MS/s, guaranteeing an ENOB > 9b with a SFDR > 74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoM approximate to 1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200 mu W and the FoM approximate to 0.1pJ/conv. This appears an attractive solution for embedded ADCI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.