A Butterworth 2nd-order programmable filter for telecommunication applications is presented. In order to operate with signals in a programmable bandwidth, the block exhibits two cut-off frequencies (in the 2MHz-to-20MHz range). A programmable gain (in the -15dB-to-9dB range) is required in order to optimize the channel performances in terms of signal-to-noise ratio. Power reduction is achieved embedding the output stage in the filter and operating the filter with two supply-voltages for the input stage (1.5V) and for the output stage (3.3V). An input common-mode feedback circuit compensates the difference between the input and output commode mode voltages. The power consumption varies from 29mW to 38mW (when the filter dc gain is -15dB), because for dc gains lower than one the input CMFB circuit is needed and his contribution in terms of power consumption has to be considered. The filter is designed in a 0.13μm CMOS technology, and performs a THD of -80dBc for a 3Vpp,diff output signal with a load of 500Ω and 10pF in parallel. The maximum output referred noise is -142dBm for a 100Ω reference-load and a 9dB dc-gain. © 2006 IEEE.
DE MATTEIS, M., D'Amico, S., Di Giandomenico, A., Hauptman, J., Baschirotto, A. (2006). A programmable double supply filter&drive block for telecommunication applications. In Research in Microelectronics and Electronics 2006, Ph.D. (pp.21-24) [10.1109/RME.2006.1689886].
A programmable double supply filter&drive block for telecommunication applications
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2006
Abstract
A Butterworth 2nd-order programmable filter for telecommunication applications is presented. In order to operate with signals in a programmable bandwidth, the block exhibits two cut-off frequencies (in the 2MHz-to-20MHz range). A programmable gain (in the -15dB-to-9dB range) is required in order to optimize the channel performances in terms of signal-to-noise ratio. Power reduction is achieved embedding the output stage in the filter and operating the filter with two supply-voltages for the input stage (1.5V) and for the output stage (3.3V). An input common-mode feedback circuit compensates the difference between the input and output commode mode voltages. The power consumption varies from 29mW to 38mW (when the filter dc gain is -15dB), because for dc gains lower than one the input CMFB circuit is needed and his contribution in terms of power consumption has to be considered. The filter is designed in a 0.13μm CMOS technology, and performs a THD of -80dBc for a 3Vpp,diff output signal with a load of 500Ω and 10pF in parallel. The maximum output referred noise is -142dBm for a 100Ω reference-load and a 9dB dc-gain. © 2006 IEEE.
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