This work introduces a design procedure for two-stage class AB opamps which minimizes power consumption for a given specifications set. The proposed procedure has been applied to the redesign of published opamps for comparison target, demonstrating the procedure validity by improving their efficiency. The systematic procedure is then applied to an opamp that will be part of the readout of an imager. The opamp is designed in a 0.35μm 3.3V standard CMOS technology and exhibits GBW=49MHz, SR=74V/ns, 0.1% settling time of 43ns, consuming only 0.87mW with a die area of 0.0053mm2.
Perenzoni, M., Malfatti, M., De Nisi, F., Stoppa, D., Baschirotto, A. (2005). A systematic design procedure for high-speed opamp performance optimization. In Proceedings of the 2005 European Conference on Circuit Theory and Design (pp.229-232). IEEE [10.1109/ECCTD.2005.1523102].
A systematic design procedure for high-speed opamp performance optimization
Baschirotto, A
2005
Abstract
This work introduces a design procedure for two-stage class AB opamps which minimizes power consumption for a given specifications set. The proposed procedure has been applied to the redesign of published opamps for comparison target, demonstrating the procedure validity by improving their efficiency. The systematic procedure is then applied to an opamp that will be part of the readout of an imager. The opamp is designed in a 0.35μm 3.3V standard CMOS technology and exhibits GBW=49MHz, SR=74V/ns, 0.1% settling time of 43ns, consuming only 0.87mW with a die area of 0.0053mm2.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
