An analog integrated front-end circuit for RDS digital decoder is described. The core of the circuit is an 8th order switched-capacitor (SC) bandpass filter at 57KHz with linear-phase response in a 3kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filter are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high performance BiCMOS technology, the circuit operates from a single 5 Volts supply and dissipates 45 mW. The die size is 5 mm<sup>2</sup>. © 1991 IEEE
Baschirotto, A., Cassis, M., Kirchlechner, P., Montecchi, F., Palmisano, G., Rossi, D. (1991). An analog BiCMOS integrated circuit for front-end RDS decoder. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 37(3), 585-591 [10.1109/30.85571].
An analog BiCMOS integrated circuit for front-end RDS decoder
BASCHIROTTO, ANDREA;
1991
Abstract
An analog integrated front-end circuit for RDS digital decoder is described. The core of the circuit is an 8th order switched-capacitor (SC) bandpass filter at 57KHz with linear-phase response in a 3kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filter are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high performance BiCMOS technology, the circuit operates from a single 5 Volts supply and dissipates 45 mW. The die size is 5 mm2. © 1991 IEEE
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