For implementation of a high-speed, radiation hardened, Charge Sensitive Preamplifier (CSP) in the monolithic 2 /spl mu/m BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Also monolithic CSPs, realized with the same technology, were irradiated and investigated. The neutron irradiation effect on the base spreading resistance (r/sub bb'/) of the CSP input NPN-transistor is shown. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. A new CSP design version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time.
Baschirotto, A., Castello, R., Pessina, G., Rancoita, P., Rattagi, M., Redaelli, M., et al. (1995). Design of a hardened fast bipolar monolithic Charge Sensitive Preamplifier. In Eighteenth Convention of Electrical and Electronics Engineers in Israel. IEEE [10.1109/EEIS.1995.513813].
Design of a hardened fast bipolar monolithic Charge Sensitive Preamplifier
BASCHIROTTO, ANDREA;Rancoita, P;
1995
Abstract
For implementation of a high-speed, radiation hardened, Charge Sensitive Preamplifier (CSP) in the monolithic 2 /spl mu/m BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Also monolithic CSPs, realized with the same technology, were irradiated and investigated. The neutron irradiation effect on the base spreading resistance (r/sub bb'/) of the CSP input NPN-transistor is shown. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. A new CSP design version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time.
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