In order to implement a high-speed, radiation hardened, charge sensitive preamplifier (CSP) in the monolithic 2 μm BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Furthermore, also monolithic CSPs, realized with the same technology, were irradiated and investigated. Results on the neutron irradiation effect on the base spreading resistance (rbb′) of the CSP input NPN-transistor are presented. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. Results confirm that the HF2CMOS process is suitable to sustain the radiation environment of the future LHC collider. A design for a new CSP version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time. © 1995.

Baschirotto, A., Castello, R., Pessina, G., Rancoita, P., Rattagi, M., Redaelli, M., et al. (1995). Design of a hardened fast bipolar monolithic Charge Sensitive Preamplifier. In Eighteenth Convention of Electrical and Electronics Engineers in Israel, 1995 (pp.2.5.5/1-2.5.5/5). IEEE [10.1109/EEIS.1995.513813].

Design of a hardened fast bipolar monolithic Charge Sensitive Preamplifier

BASCHIROTTO, ANDREA;Rancoita, P;
1995

Abstract

In order to implement a high-speed, radiation hardened, charge sensitive preamplifier (CSP) in the monolithic 2 μm BiCMOS technology (called HF2CMOS), the performance of the available NPN and PNP transistors were measured, before and after neutron irradiation. Furthermore, also monolithic CSPs, realized with the same technology, were irradiated and investigated. Results on the neutron irradiation effect on the base spreading resistance (rbb′) of the CSP input NPN-transistor are presented. Design strategies, to reduce the radiation damage effects in the CSP performance, were studied. Results confirm that the HF2CMOS process is suitable to sustain the radiation environment of the future LHC collider. A design for a new CSP version is proposed. A novel method for measuring the series noise of the CSP, at large input capacitances, was used. The method minimized the errors caused by the CSP rise-time. © 1995.
paper
2 micron; BiCMOS technology; CSP rise-time; HF2CMOS; base spreading resistance; charge sensitive preamplifier; input capacitances; neutron irradiation; radiation damage effects; radiation hardened circuit; series noise; BiCMOS analogue integrated circuits; integrated circuit noise; neutron effects; preamplifiers; pulse amplifiers; radiation hardening (electronics)
English
Convention of electrical and electronics Engineers in Israel
Eighteenth Convention of Electrical and Electronics Engineers in Israel, 1995
0-7803-2498-6
1995
2.5.5/1
2.5.5/5
none
Baschirotto, A., Castello, R., Pessina, G., Rancoita, P., Rattagi, M., Redaelli, M., et al. (1995). Design of a hardened fast bipolar monolithic Charge Sensitive Preamplifier. In Eighteenth Convention of Electrical and Electronics Engineers in Israel, 1995 (pp.2.5.5/1-2.5.5/5). IEEE [10.1109/EEIS.1995.513813].
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36896
Citazioni
  • Scopus 14
  • ???jsp.display-item.citation.isi??? ND
Social impact