This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm(2) chip area
Chironi, V., Debaillie, B., Baschirotto, A., Craninckx, J., Ingels, M. (2010). A compact digital amplitude modulator in 90nm CMOS. In 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010) (pp.702-705). Institute of Electrical and Electronics Engineers Inc. [10.1109/date.2010.5457112].
A compact digital amplitude modulator in 90nm CMOS
Baschirotto, A;
2010
Abstract
This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm(2) chip area
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