This paper examines the design and the implementation of a 6th-order bandpass ΣΔ modulator to be used for IF sampling at 10.7MHz of the FM radio signal. The modulator is sampled at 37.05MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a double-poly 0.35μm CMOS technology using Switched Capacitor (SC) technique and consumes 116mW from a single 3.3V power supply. The modulator features 75dB dynamic range and 66dB peak-SNR within a 200kHz bandwidth (FM bandwidth). Third order intermodulation products are suppressed by -78dBc
Cusinato, P., Stefani, F., Baschirotto, A. (2000). A 73dB SFDR 10.7MHz 3.3V CMOS bandpass amp;#931; amp;#916; modulator sampled at 37.05MHz. In European Solid-State Circuits Conference (pp.41-44).
A 73dB SFDR 10.7MHz 3.3V CMOS bandpass amp;#931; amp;#916; modulator sampled at 37.05MHz
BASCHIROTTO, ANDREA
2000
Abstract
This paper examines the design and the implementation of a 6th-order bandpass ΣΔ modulator to be used for IF sampling at 10.7MHz of the FM radio signal. The modulator is sampled at 37.05MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a double-poly 0.35μm CMOS technology using Switched Capacitor (SC) technique and consumes 116mW from a single 3.3V power supply. The modulator features 75dB dynamic range and 66dB peak-SNR within a 200kHz bandwidth (FM bandwidth). Third order intermodulation products are suppressed by -78dBc
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