This paper presents the trade-offs in dimensioning a 10 bit, 80 MHz current steering DAC for Wireless-LAN transmitters. All the performance parameters are considered, trying to optimize static performance, dynamic performance and area occupation. Behavioral and transistor level simulations are then used to validate the proposed mathematical analysis. ©2004 IEEE.

Baschirotto, A., Ghittori, N., Malcovati, P., Vigna, A. (2004). Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter. In Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on (pp.249-252) [10.1109/NEWCAS.2004.1359078].

Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter

BASCHIROTTO, ANDREA;
2004

Abstract

This paper presents the trade-offs in dimensioning a 10 bit, 80 MHz current steering DAC for Wireless-LAN transmitters. All the performance parameters are considered, trying to optimize static performance, dynamic performance and area occupation. Behavioral and transistor level simulations are then used to validate the proposed mathematical analysis. ©2004 IEEE.
paper
80 MHz; CMOS integrated circuits; circuit optimisation; current steering DAC; current steering digital-analog converter; dynamic performance; mathematical analysis; static performance; transistor level simulations; wireless LAN transmitters; CMOS integrated circuits; circuit simulation; digital-analogue conversion; mathematical analysis; radio transmitters; wireless LAN
English
ISCAS
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
2004
249
252
none
Baschirotto, A., Ghittori, N., Malcovati, P., Vigna, A. (2004). Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter. In Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on (pp.249-252) [10.1109/NEWCAS.2004.1359078].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36825
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