This paper describes the design and the implementation of a 6th-order bandpass ΣΔ modulator to be used for IF digitizing at 10.7 MHz of a broadcasting FM radio signal. The modulator is sampled at 37.05 MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a standard double-poly 0.35 μm CMOS technology using switched capacitor (SC) technique and consumes 116mW from a single 3.3V power supply. The modulator features 75 dB dynamic range and 66 dB peak-SNR within a 200 kHz bandwidth (FM bandwidth). Third-order intermodulation products are suppressed by -78 dBc.
Cusinato, P., Stefani, F., Baschirotto, A. (2004). A 6th-order 75dB-DR 10.7MHz 3.3V CMOS Bandpass ΣΔ Modulator sampled at 37.05MHz. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 32(4), 209-222 [10.1002/cta.277].
A 6th-order 75dB-DR 10.7MHz 3.3V CMOS Bandpass ΣΔ Modulator sampled at 37.05MHz
BASCHIROTTO, ANDREA
2004
Abstract
This paper describes the design and the implementation of a 6th-order bandpass ΣΔ modulator to be used for IF digitizing at 10.7 MHz of a broadcasting FM radio signal. The modulator is sampled at 37.05 MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a standard double-poly 0.35 μm CMOS technology using switched capacitor (SC) technique and consumes 116mW from a single 3.3V power supply. The modulator features 75 dB dynamic range and 66 dB peak-SNR within a 200 kHz bandwidth (FM bandwidth). Third-order intermodulation products are suppressed by -78 dBc.
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