High-speed low-resolution ADCs power consumption can be reduced with calibration that, however, presents some drawbacks like allocating a calibration time, calibration algorithm complexity, and calibration circuit implementation. In alternative, this paper presents a 1Gs/s 5-bit ADC without calibration, fabricated in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparator that is designed to operate with a fixed bias current. This comparator presents a reduced kickback noise, allowing increasing the input transistors sizes. This improves matching and calibration is not needed. The resulting ADC performs 4.3b-ENOB up to Nyquist frequency at 1Gs/s, while consuming 7.65mW from a 1.2V supply. The ADC FoM of about 0.39pJ/conv that is at the state-of-the-art in this resolution&sampling frequency combination. © 2011 IEEE.
D'Amico, S., Cocciolo, G., DE MATTEIS, M., Baschirotto, A. (2011). A 7.65mW 5bits 90nm 1Gs/s ADC folded interpolated without calibration. In Proceedings of the ESSCIRC 2001 (pp.151-154). IEEE [10.1109/ESSCIRC.2011.6044887].
A 7.65mW 5bits 90nm 1Gs/s ADC folded interpolated without calibration
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2011
Abstract
High-speed low-resolution ADCs power consumption can be reduced with calibration that, however, presents some drawbacks like allocating a calibration time, calibration algorithm complexity, and calibration circuit implementation. In alternative, this paper presents a 1Gs/s 5-bit ADC without calibration, fabricated in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparator that is designed to operate with a fixed bias current. This comparator presents a reduced kickback noise, allowing increasing the input transistors sizes. This improves matching and calibration is not needed. The resulting ADC performs 4.3b-ENOB up to Nyquist frequency at 1Gs/s, while consuming 7.65mW from a 1.2V supply. The ADC FoM of about 0.39pJ/conv that is at the state-of-the-art in this resolution&sampling frequency combination. © 2011 IEEE.
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