A 1.2V 600μW SC double-sampled pseudodifferential Sample&Hold circuit is realized in a standard 0.5μm CMOS technology without using on-chip voltage multiplier. With a 600m Vpp signal at 2MHz using a 40MHz sampling frequency, the S&H exhibits a THD better than -50dB and a CMR better than -40dB. © 1998 Editions Frontieres.
Baschirotto, A. (1998). A 40MHz CMOS sample hold operating at 1.2V. In Proceedings of the 24th European Solid-State Circuits Conference, 1998. ESSCIRC '98 (pp.248-251). IEEE [10.1109/ESSCIR.1998.186255].
A 40MHz CMOS sample hold operating at 1.2V
BASCHIROTTO, ANDREA
1998
Abstract
A 1.2V 600μW SC double-sampled pseudodifferential Sample&Hold circuit is realized in a standard 0.5μm CMOS technology without using on-chip voltage multiplier. With a 600m Vpp signal at 2MHz using a 40MHz sampling frequency, the S&H exhibits a THD better than -50dB and a CMR better than -40dB. © 1998 Editions Frontieres.
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