A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatch

Samori, C., Baschirotto, A., Liberali, V. (1995). Two-path structure for high performance sigma-delta modulators. ELECTRONICS LETTERS, 31(19), 1624-1625 [10.1049/el:19951155].

Two-path structure for high performance sigma-delta modulators

BASCHIROTTO, ANDREA;
1995

Abstract

A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatch
Articolo in rivista - Articolo scientifico
idle clock phase; nonideality compensation; oversampling sampling ratio; parallel time-interleaved architecture; path mismatch sensitivity; second-order SC modulator; sigma-delta modulators; two-path structure; parallel architectures; sigma-delta modulation; switched capacitor networks
English
1995
31
19
1624
1625
none
Samori, C., Baschirotto, A., Liberali, V. (1995). Two-path structure for high performance sigma-delta modulators. ELECTRONICS LETTERS, 31(19), 1624-1625 [10.1049/el:19951155].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36774
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