A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatch
Samori, C., Baschirotto, A., Liberali, V. (1995). Two-path structure for high performance sigma-delta modulators. ELECTRONICS LETTERS, 31(19), 1624-1625 [10.1049/el:19951155].
Two-path structure for high performance sigma-delta modulators
BASCHIROTTO, ANDREA;
1995
Abstract
A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatchFile in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.