A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists in compensating the driver non-linearity with an opposite load non-linearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance are optimized for any operation condition. A prototype cell has been designed in a standard 0.5 μm CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q = 1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance are kept lower that 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mW.

Baschirotto, A., Baschirotto, U., Castello, R. (2000). High-frequency CMOS low-power single-branch continuous-time filters. In ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY (pp.577-580). IEEE [10.1109/ISCAS.2000.856394].

High-frequency CMOS low-power single-branch continuous-time filters

Baschirotto, A;
2000

Abstract

A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists in compensating the driver non-linearity with an opposite load non-linearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance are optimized for any operation condition. A prototype cell has been designed in a standard 0.5 μm CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q = 1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance are kept lower that 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mW.
paper
Capacitance measurement; Digital filters; Energy utilization; Integrated circuit layout; Linear network analysis; Linear network synthesis; Linearization; MOS devices; Poles and zeros
English
IEEE International Symposium on Circuits and Systems (ISCAS 2000) MAY 28-31
2000
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY
2000
2
577
580
none
Baschirotto, A., Baschirotto, U., Castello, R. (2000). High-frequency CMOS low-power single-branch continuous-time filters. In ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY (pp.577-580). IEEE [10.1109/ISCAS.2000.856394].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36768
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