An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital ΣΔ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB.
Annovazzi, M., Colonna, V., Gandolfi, G., Stefani, F., Baschirotto, A. (2002). A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37(7), 825-834 [10.1109/JSSC.2002.1015679].
A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology
BASCHIROTTO, ANDREA
2002
Abstract
An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital ΣΔ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB.
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