In this paper a 13b Incremental A/D converter for High-Linearity sensors read-out applications is described and characterized. The incremental solution is preferred to traditional ΣΔ architectures to simplify the decimator Alter topology, which is actually a single bit digital accumulator. This leads to lower area occupancy and power consumption. The input signal, which can be connected either in single-ended or differential mode, is sampled by a resettable SC integrator, followed by a discrete time comparator, which selects the feedback signal. The silicon prototype has been designed in 0.35μm technology with a power supply of 3.3V and consumes 95μW with throughput rate of 120Hz. The measurements results show an ENOB of 12.41 bits. The chip area is 0.22mm2. © 2007 IEEE.

Ferragina, V., Ferri, M., Grassi, M., Rossini, A., Malcovati, P., Baschirotto, A. (2007). A 12.4 ENOB incremental A/D converter for high-linearity sensors read-out applications. In Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (pp.3582-3585). Institute of Electrical and Electronics Engineers Inc. [10.1109/ISCAS.2007.378527].

A 12.4 ENOB incremental A/D converter for high-linearity sensors read-out applications

BASCHIROTTO, ANDREA
2007

Abstract

In this paper a 13b Incremental A/D converter for High-Linearity sensors read-out applications is described and characterized. The incremental solution is preferred to traditional ΣΔ architectures to simplify the decimator Alter topology, which is actually a single bit digital accumulator. This leads to lower area occupancy and power consumption. The input signal, which can be connected either in single-ended or differential mode, is sampled by a resettable SC integrator, followed by a discrete time comparator, which selects the feedback signal. The silicon prototype has been designed in 0.35μm technology with a power supply of 3.3V and consumes 95μW with throughput rate of 120Hz. The measurements results show an ENOB of 12.41 bits. The chip area is 0.22mm2. © 2007 IEEE.
paper
0.35 micron; 12.41 bit; 13 bit; 3.3 V; 950 muW; SigmaDelta architectures; decimator filter topology; digital accumulator; discrete time comparator; high-linearity sensors read-out; incremental A/D converter; silicon prototype; analogue-digital conversion; comparators (circuits); silicon
English
2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
2007
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
1-4244-0920-9
2007
3582
3585
4253455
none
Ferragina, V., Ferri, M., Grassi, M., Rossini, A., Malcovati, P., Baschirotto, A. (2007). A 12.4 ENOB incremental A/D converter for high-linearity sensors read-out applications. In Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (pp.3582-3585). Institute of Electrical and Electronics Engineers Inc. [10.1109/ISCAS.2007.378527].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36763
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