In this paper we present a 1.6-GHz pipeline A/D converter (ADC) for digital television and digital broadcast satellite. The ADC, designed in a standard 65-nm CMOS technology, achieves in simulation a signal-to-noise and distortion ratio (SNDR) of 54.3 dB (8.73 ENOB), over a signal bandwidth of 615 MHz. The ADC core consumes 430 mW from 1-V and 2.5-V power supplies. In order to achieve the required sampling frequency, the proposed ADC exploits a time-interleaved architecture with four paths. Each path consists of a 10-bit pipeline ADC with four stages (a 3.5-bit stage, a 1.5-bit stage, a 2.5-bit stage and a final 4-bit flash stage). Operational amplifier sharing is adopted in the last two stages for reducing the power consumption. The active area of the chip is 2.7 × 3:2 mm2. ©2010 IEEE.

Picolli, L., Crespi, L., Chaahoub, F., Malcovati, P., & Baschirotto, A. (2010). A 1.6-GHz, 54-dB signal-to-noise and distortion ratio pipeline A/D converter. In Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on (pp.1735-1738) [10.1109/ISCAS.2010.5537541].

A 1.6-GHz, 54-dB signal-to-noise and distortion ratio pipeline A/D converter

BASCHIROTTO, ANDREA
2010

Abstract

In this paper we present a 1.6-GHz pipeline A/D converter (ADC) for digital television and digital broadcast satellite. The ADC, designed in a standard 65-nm CMOS technology, achieves in simulation a signal-to-noise and distortion ratio (SNDR) of 54.3 dB (8.73 ENOB), over a signal bandwidth of 615 MHz. The ADC core consumes 430 mW from 1-V and 2.5-V power supplies. In order to achieve the required sampling frequency, the proposed ADC exploits a time-interleaved architecture with four paths. Each path consists of a 10-bit pipeline ADC with four stages (a 3.5-bit stage, a 1.5-bit stage, a 2.5-bit stage and a final 4-bit flash stage). Operational amplifier sharing is adopted in the last two stages for reducing the power consumption. The active area of the chip is 2.7 × 3:2 mm2. ©2010 IEEE.
No
paper
Scientifica
CMOS technology; digital broadcast satellite; digital television; distortion ratio; frequency 1.6 GHz; noise figure 54 dB; operational amplifier; pipeline A/D converter; power 430 mW; signal-to-noise; wavelength 65 nm; CMOS integrated circuits; analogue-digital conversion; operational amplifiers; television
English
ISCAS
978-1-4244-5308-5
Picolli, L., Crespi, L., Chaahoub, F., Malcovati, P., & Baschirotto, A. (2010). A 1.6-GHz, 54-dB signal-to-noise and distortion ratio pipeline A/D converter. In Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on (pp.1735-1738) [10.1109/ISCAS.2010.5537541].
Picolli, L; Crespi, L; Chaahoub, F; Malcovati, P; Baschirotto, A
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/10281/36759
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