In this paper, we propose a transmitter baseband architecture for the present and up-coming WLAN applications (IEEE 802.11a/g, 802.11n, 802.16), based on a 600-MS/s current-steering DAC with a passive output load, to perform the baseband signal processing, avoiding the use of any active analog reconstruction filter. The DAC, fabricated in a 0.13-μm CMOS technology, consumes 2.4 mW from a 1.2-V single supply voltage. The DAC exhibits 68 dB of SFDR at full-scale for a 12-MHz input signal frequency and 9.7 bits of full-scale dynamic range in the bandwith from dc to 10 MHz. © 2008 Springer Science+Business Media, LLC.
Ghittori, N., Vigna, A., Malcovati, P., D'Amico, S., Baschirotto, A. (2009). An IEEE 802.11 and 802.16 WLAN Wireless transmitter baseband architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 59, 231-242 [10.1007/s10470-008-9262-x].
An IEEE 802.11 and 802.16 WLAN Wireless transmitter baseband architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC
BASCHIROTTO, ANDREA
2009
Abstract
In this paper, we propose a transmitter baseband architecture for the present and up-coming WLAN applications (IEEE 802.11a/g, 802.11n, 802.16), based on a 600-MS/s current-steering DAC with a passive output load, to perform the baseband signal processing, avoiding the use of any active analog reconstruction filter. The DAC, fabricated in a 0.13-μm CMOS technology, consumes 2.4 mW from a 1.2-V single supply voltage. The DAC exhibits 68 dB of SFDR at full-scale for a 12-MHz input signal frequency and 9.7 bits of full-scale dynamic range in the bandwith from dc to 10 MHz. © 2008 Springer Science+Business Media, LLC.
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