This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35um CMOS technology and the conversion period is lower than 500ns (i.e. 2MHz data rate). The power consumption is 39mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2.
Picolli, L., Maloberti, F., Rossini, A., Borghetti, F., Malcovati, P., Baschirotto, A. (2006). A 10-bit pipeline A/D converter without timing signals. In Proceedings - IEEE International Symposium on Circuits and Systems (pp.5355-5358). IEEE [10.1109/ISCAS.2006.1693843].
A 10-bit pipeline A/D converter without timing signals
BASCHIROTTO, ANDREA
2006
Abstract
This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35um CMOS technology and the conversion period is lower than 500ns (i.e. 2MHz data rate). The power consumption is 39mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2.
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