In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm 2. © 2009 Springer Science+Business Media, LLC.
Malcovati, P., Picolli, L., Crespi, L., Chaahoub, F., Baschirotto, A. (2010). A 90-nm CMOS, 8-Bit Pipeline ADC with 60-MHz Bandwidth and 125-MS/s or 250-MS/s Sampling Frequency. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 64(2), 159-172 [10.1007/S10470-009-9445-0].
A 90-nm CMOS, 8-Bit Pipeline ADC with 60-MHz Bandwidth and 125-MS/s or 250-MS/s Sampling Frequency
BASCHIROTTO, ANDREA
2010
Abstract
In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm 2. © 2009 Springer Science+Business Media, LLC.
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