For the present and up-coming WLAN applications (802.11a/g, 802.11n, 802.16), a transmission baseband architecture uses a 600-MS/s current-steering DAC with a passive output load to perform the baseband signal processing, avoiding the use of any active reconstruction filter. In a 0.13-μm CMOS technology the DAC consumes 2.4 mW from a single 1.2-V supply voltage. The DAC exhibits a full-scale SFDR of 68 dB for an input signal frequency of 12 MHz and a full-scale dynamic range of 9.7 bits between 0 and 10 MHz. These data correspond to the best reported Figure of Merit, if compared with state-of-the-art digital-to-analog converters.
Ghittori, N., Vigna, A., Malcovati, P., D'Amico, S., Baschirotto, A. (2006). A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN 802.11 and 802.16 wireless transmitters. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (pp.404-407). 345 E 47TH ST, NEW YORK, NY 10017 USA : IEEE [10.1109/ESSCIR.2006.307616].
A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN 802.11 and 802.16 wireless transmitters
BASCHIROTTO, ANDREA
2006
Abstract
For the present and up-coming WLAN applications (802.11a/g, 802.11n, 802.16), a transmission baseband architecture uses a 600-MS/s current-steering DAC with a passive output load to perform the baseband signal processing, avoiding the use of any active reconstruction filter. In a 0.13-μm CMOS technology the DAC consumes 2.4 mW from a single 1.2-V supply voltage. The DAC exhibits a full-scale SFDR of 68 dB for an input signal frequency of 12 MHz and a full-scale dynamic range of 9.7 bits between 0 and 10 MHz. These data correspond to the best reported Figure of Merit, if compared with state-of-the-art digital-to-analog converters.
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