A time-to-voltage converter is proposed which is based on a single ramp system. In contrast to other approaches, the time-to-voltage gain is made dependent on capacitance matching rather than on the absolute accuracy of the capacitors used.

Baschirotto, A., Boella, G., Castello, R., Frattini, G., Pessina, G., Rancoita, P. (1998). 3 ns resolution CMOS low-power time-to-voltage converter. ELECTRONICS LETTERS, 34(7), 614-615 [10.1049/el:19980437].

3 ns resolution CMOS low-power time-to-voltage converter

BASCHIROTTO, ANDREA;Pessina, G;
1998

Abstract

A time-to-voltage converter is proposed which is based on a single ramp system. In contrast to other approaches, the time-to-voltage gain is made dependent on capacitance matching rather than on the absolute accuracy of the capacitors used.
Articolo in rivista - Articolo scientifico
3 ns; CMOS low-power converter; capacitance matching; single ramp system; time-to-voltage converter; CMOS analogue integrated circuits; convertors
English
1998
34
7
614
615
none
Baschirotto, A., Boella, G., Castello, R., Frattini, G., Pessina, G., Rancoita, P. (1998). 3 ns resolution CMOS low-power time-to-voltage converter. ELECTRONICS LETTERS, 34(7), 614-615 [10.1049/el:19980437].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36713
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