This paper is concerned with the impact of technology scaling on the choice of A/D converters in telecom receivers. It is shown that the trend of diminishing feature size, together with better matching of passive components, allows the use of A/D topologies traditionally confined to low-frequency, medium-resolution applications. The design of a 10 bit 20 MS/s ADC using the successive approximation algorithm is presented in order to validate the presented concepts. By using a deep-submicron technology, the speed of the chosen architecture is pushed to meet the desired output rate.
Nielsen, J., Malcovati, P., Baschirotto, A. (2005). Technology scaling impact on embedded ADC design for telecom receivers. In IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 (pp.4614-4617). Institute of Electrical and Electronics Engineers Inc. [10.1109/ISCAS.2005.1465660].
Technology scaling impact on embedded ADC design for telecom receivers
Baschirotto, A
2005
Abstract
This paper is concerned with the impact of technology scaling on the choice of A/D converters in telecom receivers. It is shown that the trend of diminishing feature size, together with better matching of passive components, allows the use of A/D topologies traditionally confined to low-frequency, medium-resolution applications. The design of a 10 bit 20 MS/s ADC using the successive approximation algorithm is presented in order to validate the presented concepts. By using a deep-submicron technology, the speed of the chosen architecture is pushed to meet the desired output rate.
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