In this paper a novel 10-bit pipeline A/D converter for low noise, self-triggered sensors is presented. The main innovative feature of the proposed A/D structure is the concept that a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock) in order to produce the conversion (assuming that a sampled signal is provided at the input). This concept is validated by the experimental results here reported. A prototype ADC has been fabricated in a standard 0.35 mu m CMOS technology, has an active area of 2.24mm(2), provides a conversion in 2.5 mu s (400kS/s) and consumes 14mW from a 2.3V power supply
Picolli, L., Rossini, A., Malcovati, P., Maloberti, F., Baschirotto, A. (2006). A Clock-Less 10-bit Pipeline A/D Converter for Self-Triggered Sensors. In ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (pp.384-387). 345 E 47TH ST, NEW YORK, NY 10017 USA : IEEE [10.1109/ESSCIR.2006.307611].
A Clock-Less 10-bit Pipeline A/D Converter for Self-Triggered Sensors
BASCHIROTTO, ANDREA
2006
Abstract
In this paper a novel 10-bit pipeline A/D converter for low noise, self-triggered sensors is presented. The main innovative feature of the proposed A/D structure is the concept that a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock) in order to produce the conversion (assuming that a sampled signal is provided at the input). This concept is validated by the experimental results here reported. A prototype ADC has been fabricated in a standard 0.35 mu m CMOS technology, has an active area of 2.24mm(2), provides a conversion in 2.5 mu s (400kS/s) and consumes 14mW from a 2.3V power supply
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