This brief presents a 4th-order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 $mu ext{W}$ power (408 $mu ext{W}$ per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 $mu ext{V}_{mathrm{ RMS}}$ output noise, and at 0.32 V0-PEAK differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$.
De Matteis, M., Galante, N., Fary, F., Vallicelli, E., Baschirotto, A. (2021). 64 dB Dynamic-Range 810 μw 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, 68(9), 3068-3072 [10.1109/TCSII.2021.3095971].
64 dB Dynamic-Range 810 μw 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS
De Matteis M.
;Fary F.
;Vallicelli E.;Baschirotto A.
2021
Abstract
This brief presents a 4th-order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 $mu ext{W}$ power (408 $mu ext{W}$ per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 $mu ext{V}_{mathrm{ RMS}}$ output noise, and at 0.32 V0-PEAK differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
