This paper presents the design and the characterization of an integrated wide-range interface circuit for resistive sensors. The device is actually a multi-scale transresistance continuous time amplifier followed by a 13-bit incremental A/D converter. As shown in measurements the worst case resolution is near to 0.1% over a range of 5.3 decades [100Ω-20MΩ] thanks to a calibration technique which cancels offset and gain error mismatch between scales. The chip has been designed in 0.35μm CMOS technology.

Grassi, M., Malcovati, P., & Baschirotto, A. (2005). A 0.1% accuracy 100Ω-20MΩ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output. In Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference (pp.351-354). IEEE [10.1109/ESSCIR.2005.1541632].

A 0.1% accuracy 100Ω-20MΩ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output

BASCHIROTTO, ANDREA
2005

Abstract

This paper presents the design and the characterization of an integrated wide-range interface circuit for resistive sensors. The device is actually a multi-scale transresistance continuous time amplifier followed by a 13-bit incremental A/D converter. As shown in measurements the worst case resolution is near to 0.1% over a range of 5.3 decades [100Ω-20MΩ] thanks to a calibration technique which cancels offset and gain error mismatch between scales. The chip has been designed in 0.35μm CMOS technology.
No
paper
Scientifica
0.35 micron; 100 to 20E6 ohm; 13 bit; A/D converter; CMOS technology; continuous time amplifier; integrated gas sensor; multiscale transresistance amplifier; resistive sensors; wide-range interface circuit; CMOS integrated circuits; amplifiers; analogue-digital conversion; calibration; gas sensors; integrated circuit design;
English
ESSCIRC 2005: 31st European Solid-State Circuits Conference - 12 September 2005 through 16 September 2005
9780780392052
Grassi, M., Malcovati, P., & Baschirotto, A. (2005). A 0.1% accuracy 100Ω-20MΩ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output. In Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference (pp.351-354). IEEE [10.1109/ESSCIR.2005.1541632].
Grassi, M; Malcovati, P; Baschirotto, A
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/35319
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